HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 399

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
9.5.2
(1)
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle.
Basic Timing
Normal Space Interface
Figure 9.3
Note: * The waveform for DACKn is when active low is specified.
Read
Write
Normal Space Basic Access Timing (Access Wait 0)
WEn(BEn)
RD/WR
RD/WR
DACKn
CKIO
CSn
RD
BS
A
D
D
*
T1
Rev. 3.00 Jan. 18, 2008 Page 337 of 1458
T2
Section 9
Bus State Controller (BSC)
REJ09B0033-0300

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