HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 668
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Section 18
Note:
Rev. 3.00 Jan. 18, 2008 Page 606 of 1458
REJ09B0033-0300
Bit
0
*
Bit Name
DR
The only value that can be written is 0 to clear the flag.
Serial Communication Interface with FIFO (SCIF)
Initial Value
0
R/W
R/(W)* Receive Data Ready
Description
Indicates that the receive FIFO data register
(SCFRDR) stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit in asynchronous mode.
0: Receive is in progress, or no received data
[Clearing conditions] (Initial value)
•
•
1: Next receive data is not received
[Setting condition]
SCFRDR stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit.*
Note:
remains in SCFRDR after the receive ended
normally.
Power-on reset, manual reset
All receive data in SCFRDR is read, and DR is
read as 1, then written to with 0.
*
This is equivalent to 1.5 frames with the
8-bit 1-stop-bit format. (etu: Element
Time Unit)
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