HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 331

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 8
Interrupt Controller (INTC)
• Realtime clock (RTC)
• A/D converter (ADC)
• PC card controller (PCC)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except H-UDI by writing to the interrupt
priority registers A, B, and E to J (IPRA, IPRB, and IPRE to IPRJ). The priority level of the H-
UDI interrupt is 15 (fixed).
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
8.4.6
Interrupt Exception Handling and Priority
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The
priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and
level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt
request is ignored.
Tables 8.3 and 8.4 list the interrupt sources, the codes for the interrupt event registers (INTEVT
and INTEVT2), and the interrupt priority.
Each interrupt source is assigned a unique code by INTEVT and INTEVT2. The start address of
the exception handling routine is common for each interrupt source. This is why, for instance, the
value of INTEVT or INTEVT2 is used as an offset at the start of the exception handling routine
and branched to in order to identify the interrupt source.
IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15
for each module by setting interrupt priority registers A to J (IPRA to IPRJ). A reset assigns
priority level 0 to IRQ and on-chip peripheral module interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in tables 8.3 and 8.4.
Rev. 3.00 Jan. 18, 2008 Page 269 of 1458
REJ09B0033-0300