HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1160

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 31
31.5.2
For transfer with DMAC, set MMCIF (DMACR) after setting DMAC. The FIFO ready flag is
generated after DMACR is set and data more than threshold set in DMACR is written to the FIFO.
Start transmission to the MMC after setting the flag. Figures 31.28 to 31.31 show the operational
flowcharts for write sequence in MMC mode.
• FIFO is cleared.
• Write command is transmitted.
• DMACR is set and write data is set to the FIFO.
• Confirmed that the data more than DMACR setting condition is written to the FIFO by the
• The end of the transfer with the DMAC is confirmed, and 0 is set to the DMAEN bit in
• When the CRC error (CRCERI) or the command timeout error (CTERI) occurs during
• When the CRC error (CRCERI), write error (WRERI), or data timeout error (DTERI) occurs
When the DMA is in use, an interrupt between blocks in pre-defined multiblock transfer can be
processed by hard by setting the AUTO bit in DMACR to 1. Figure 31.32 shows the operational
flowchart for pre-defined multi write sequence in MMC mode.
• FIFO is cleared.
• The number of blocks is set to TBNCR.
• The START bit in CMDSTRT is set to 1 and command transmission is started.
• Command response is received from the MMC.
• If the MMC does not return the command response, it detected by the command timeout error
• DMACR is set and write data is set to the FIFO.
• The end of the transfer with the DMAC is confirmed, and 0 is set to the DMAEN bit in
• Command sequence end is detected by polling the BUSY flag in CSTR or the multiblock
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FIFO ready flag (FRDYI), or that all data is written to the FIFO by the DMAC, and then the
DATAEN bit in OPCR is set to 1 to start write data transmission.
DMACR.
command response reception, write 1 to the CMDOFF bit.
during write data transmission, 1 is written to the CMDOFF bit and DMACR is set to H'00 to
clear the FIFO.
flag (CTERI).
DMACR.
transfer (pre-defined) end flag (BTI).
Operation of Write Sequence
MultiMediaCard Interface (MMCIF)