HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 841

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

24.3.7
USBHHCCA includes physical addresses of the host controller communication area. The host
controller driver determines the alignment limitation by writing 1 to all bits in USBHHCCA and
by reading the content of USBHHCCA. Alignment is evaluated by checking the number of 0 in
the lower bits. The minimum alignment is 256 bytes. Consequently, bits 0 to 7 must be always
returned to 0 when they are read. This area is used to retain the control structure and interrupt table
that are accessed by the host controller and host controller driver.
24.3.8
USBHPCED includes a physical address of current Isochronous ED or Interrupt ED.
Bit
31 to 8
7 to 0
Bit
31 to 4
3 to 0
HCCA Register (USBHHCCA)
Hc Period Current ED Register (USBHPCED)
Bit Name
HCCA23 to
HCCA0

Bit Name
PCED27 to
PCED0

Initial
Value
All 0
All 0
Initial
Value
All 0
All 0
R/W
R
R/W
R
R
R/W
Description
HCCA
Physical addresses of the host controller communication
area
Reserved
These bits are always read as 0. The write value should
always be 0.
Description
PCED
Physical address of current Isochronous ED or Interrupt
ED
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 779 of 1458
Section 24
USB Host Controller (USBH)
REJ09B0033-0300