HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 663

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
8
7
Bit Name Initial Value R/W
TSF
ER
0
0
R/(W)* Transmit Data Stop Flag
R/(W)* Receive Error
Description
Indicates that the number of transmit data matches the
value set in SCTDSR.
0: Transmit data number does not match the value set
[Clearing conditions]
•
•
1: Transmit data number matches the value set in
Indicates that a framing error or parity error occurred
during reception in asynchronous mode.*
0: Receive is normally completed without any framing or
[Clearing conditions]
Power-on reset, manual reset
ER is read as 1, then written to with 0.
1: A framing error or a parity error has occurred during
[Setting conditions]
•
•
Notes: 1. Indicates clearing the RE bit to 0 in SCSCR
Section 18
in SCTDSR
receiving
SCTDSR
parity error
Power-on reset, manual reset
Writing 0 after reading TSF = 1
The stop bit is 0 after checking whether or not the
last stop bit of the received data is 1 at the end of
one-data receive.*
The total number of 1's in the received data and in
the parity bit does not match the even/odd parity
specification specified by the O/E bit in the SCSMR.
2. n the stop mode, only the first stop bit is
does not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the received data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCRDR includes a receive error can
be detected by the FER and PER bits in
SCSSR.
checked; the second stop bit is not checked.
Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Jan. 18, 2008 Page 601 of 1458
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REJ09B0033-0300
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