HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 231

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HD6417320

Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
(c)
The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.
Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with
0s creates the address in the corresponding physical address space.
(d) P4 Area
The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache
and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.
H'8000 0000
H'A000 0000
H'C000 0000
H'E000 0000
H'FFFF FFFF
H'0000 0000
P2 Area
256
Address translation not possible
Address translation not possible
Address translation not possible
Address translation possible
Address translation possible
Privileged mode
Non-Cacheable
Non-Cacheable
Cacheable
Cacheable
Cacheable
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)
P3 area
P0 area
P1 area
P2 area
P4 area
External Address
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
Space
256
Section 4 Memory Management Unit (MMU)
Rev. 3.00 Jan. 18, 2008 Page 169 of 1458
Address translation possible
User mode
Address error
Address error
Cacheable
Uxy area*
U0 area
Note: Only exists when SR.DSP = 1
REJ09B0033-0300
H'8000 0000
H'A500 0000
H'A5FF FFFF
H'FFFF FFFF
H'0000 0000

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