HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 108

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
2.3.2
The system registers: multiply and accumulate registers (MACH/MACL) and procedure register
(PR) as system registers can be accessed by the LDS and STS instructions.
(1)
The multiply and accumulate registers (MACH/MACL) store the results of multiplication and
accumulation instructions or multiplication instructions. The MACH/MACL registers also store
addition values for the multiplication and accumulations. After reset, these registers are undefined.
The MACH and MACL registers store upper 32 bits and lower 32 bits, respectively.
(2)
The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF,
or JSR instruction. The return address stored in the PR register is restored to the program counter
(PC) by the RTS (return from the subroutine) instruction. After reset, this register is undefined.
Rev. 3.00 Jan. 18, 2008 Page 46 of 1458
REJ09B0033-0300
Multiply and Accumulate Registers (MACH/MACL)
Procedure Register (PR)
System Registers
31
CPU
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
*1,*2
*2
*2
*2
*2
*2
*2
*2
Figure 2.4
0
General Registers: Undefined after reset
Notes: 1. R0 functions as an index register in the indexed
General Registers
2. R0 to R7 are banked registers. In privileged
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some
instructions, only R0 can be used as the source
or destination register.
mode, either R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1 is selected by the
RB bit in the SR register.