HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1179

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

33.2.5
BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address
specified by BARB.
33.2.6
BDRB is a 32-bit readable/writable register. The control bits CDB1, CDB0, XYE, and XYS in the
break bus cycle register (BBRB) select one of the four data buses for break condition B.
Bit
31 to 0 BAMB31 to
Bit
31 to 0 BDB31 to
Bit Name
BAMB0
Bit Name
BDB0
Break Address Mask Register B (BAMRB)
Break Data Register B (BDRB)
Initial
Value
All 0
Initial
Value
All 0
R/W
R/W
R/W
R/W
Description
Break Address Mask B
Specifies bits masked in the break address of channel
B specified by BARB (BAB31 to BAB0).
0: Break address BABn of channel B is included in the
1: Break address BABn of channel B is masked and is
Note: n = 31 to 0
Description
Break Data Bit B
Stores data which specifies a break condition in
channel B.
If the I bus is selected in BBRB, the break data on IDB
is set in BDB31 to BDB0.
If the L bus is selected in BBRB, the break data on LDB
is set in BDB31 to BDB0.
If the X memory is selected in BBRB, the break data in
bits 15 to 0 in XDB is set in BDB31 to BDB16. In this
case, the values in BDB15 to BDB0 are arbitrary.
If the Y memory is selected in BBRB, the break data in
bits 15 to 0 in YDB are set in BDB15 to BDB0. In this
case, the values in BDB31 to BDB16 are arbitrary.
break condition
not included in the break condition
Rev. 3.00 Jan. 18, 2008 Page 1117 of 1458
Section 33 User Break Controller (UBC)
REJ09B0033-0300