HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 767

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit
11
10
9
8
7
6
5, 4
3
2
1
0
Bit Name
TDLA3
TDLA2
TDLA1
TDLA0
TDRE
TLREP

TDRA3
TDRA2
TDRA1
TDRA0
Initial
Value
0
0
0
0
0
0
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Description
Transmit Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Transmit Right-Channel Data Enable
0: Disables right-channel data transmission
1: Enables right-channel data transmission
Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
1: Repeatedly transmits data specified in the SITDL bit
•
•
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
as right-channel data
in SITDR as right-channel data
Transmit data for the left channel is specified in the
SITDL bit in SITDR.
This bit setting is valid when the TDRE bit is set to
1.
When this bit is set to 1, the SITDR settings are
ignored.
Transmit data for the right channel is specified in
the SITDR bit in SITDR.
Rev. 3.00 Jan. 18, 2008 Page 705 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300