HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 755

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

21.3.7
SISTR is a 16-bit read-only register that shows the SIOF state. Each bit in this register becomes an
SIOF interrupt source when the corresponding bit in SIIER is set to 1.
SISTR is initialized in module stop mode.
Bit
15
14
13
Bit Name

TCRDY
TFEMP
Status Register (SISTR)
Initial
Value
0
0
0
R/W
R
R
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Transmit Control Data Ready
0: Indicates that a write to SITCR is disabled
1: Indicates that a write to SITCR is enabled
•
•
•
•
Transmit FIFO Empty
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
•
•
•
If SITCR is written when this bit is cleared to 0, SITCR
is over-written and the previous contents of SITCR
are not output from the SIOFTxD pin.
This bit is valid when the TXE bit in SITCR is set to 1.
This bit indicates a state of the SIOF. If SITCR is
written, the SIOF clears this bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
This bit is valid when the TXE bit in SICTR is 1.
This bit indicates a state; if SITDR is written, the SIOF
clears this bit.
If the issue of interrupts by this bit is enabled, an
SIOF interrupt is issued.
Rev. 3.00 Jan. 18, 2008 Page 693 of 1458
Section 21
Serial I/O with FIFO (SIOF)
REJ09B0033-0300