HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 889

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

25.3.32 Endpoint Stall Register 0 (EPSTL0)
EPSTL stalls each endpoint. The endpoint in which the stall bit is set to 1 returns a stall handshake
to the host from the next transfer when 1 is written to. The stall bit for endpoint 0 is cleared
automatically on reception of 8 byte command data for which decoding is performed by the
function and the EP0 STL bit is cleared. When the SETUPTS flag bit in the IFR0 register is set to
1, a write of the EP0 STL bit to 1 is ignored. For detailed operation, see section 25.8, Stall
Operations.
Bit
1
0
Bit
7 to 4 
3
2
1
0
Bit Name
EP2 DMAE
EP1 DMAE
Bit Name
EP3 STL
EP2 STL
EP1 STL
EP0 STL
Initial Value R/W
All 0
0
0
0
0
0
0
Initial Value R/W Description
R
R/W
R/W
R/W
R/W
R/W EP2DMA Enable
R/W EP1DMAE Enable
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
EP3 Stall
Sets EP3 stall
EP2 Stall
Sets EP2 stall
EP1 Stall
Sets EP1 stall
EP0 Stall
Sets EP0 stall
Enables DMA transfer for EP2.
Enables DMA transfer for EP1.
Section 25
Rev. 3.00 Jan. 18, 2008 Page 827 of 1458
USB Function Controller (USBF)
REJ09B0033-0300