HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 39

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Figure 10.20 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
Section 11 Clock Pulse Generator (CPG)
Figure 11.1 Block Diagram of CPG ........................................................................................... 454
Figure 11.2 Points for Attention when Using Crystal Resonator................................................ 467
Figure 11.3 Points for Attention when Using PLL Oscillator Circuit ........................................ 468
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT .......................................................................................... 470
Figure 12.2 Writing to WTCNT and WTCSR............................................................................ 474
Section 13 Power-Down Modes
Figure 13.1 Canceling Standby Mode with STBY Bit in STBCR.............................................. 490
Figure 13.2 STATUS Output at Power-on Reset........................................................................ 492
Figure 13.3 STATUS Output at Manual Reset ........................................................................... 492
Figure 13.4 STATUS Output when Software Standby Mode is Canceled by an Interrupt......... 493
Figure 13.5 STATUS Output When Software Standby Mode is Canceled
Figure 13.6 STATUS Output When Software Standby Mode is Canceled
Figure 13.7 STATUS Output when Sleep Mode is Canceled by an Interrupt ............................ 494
Figure 13.8 STATUS Output When Sleep Mode is Canceled by a Power-on Reset.................. 495
Figure 13.9 STATUS Output When Sleep Mode is Canceled by a Manual Reset ..................... 495
Figure 13.10 Hardware Standby Mode Timing (CA is pulled low in normal operation) ........... 497
Figure 13.11 Hardware Standby Mode Timing
Figure 13.12 Timing When Power of Pins other than V
by a Power-on Reset................................................................................................ 493
by a Manual Reset ................................................................................................... 494
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time) ........................................ 450
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally)................................................... 450
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time) ........................................ 451
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally)................................................... 452
(CA is pulled low while WDT operates after the standby mode is canceled) ....... 498
CC
_RTC and V
Rev. 3.00 Jan. 18, 2008 Page xxxix of lxii
CC
Q_RTC is Off........... 498