HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1477

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
(2) Reception in Master Mode
21.4 Operation
21.4.10 SPI Mode
21.5 Usage Notes
Table 21.11 Transmit and
Receive Reset
Page Revision (See Manual for Details)
722
725
734
Figure 21.10 replaced.
Added Note 1 to 4
Notes: Refer to the following procedure to operate the
transmit reset/receive reset.
1. Set the master clock source in peripheral clock.
2. Set prescaler count value of the baud rate generator
3. Set division ratio in borate generator's output level
4. Reset transmit/receive operation. (Write "1", to
Deleted
Added
(Write 1 (master clock = Pf (peripheral clock)) to
MSSEL bit in the SISCR register).
by1/1. (Write "00000" (division ratio= 1/1) to the
BRPS bits 4 to 0 in SISCR register).
by 1/1. (Write "111" (division ratio=1/1) to the BRDV
bits 2 to 0 in SISCR register).
reset, to TXRST or RXRST bit in the SICTR
register).
10
11
12
8
9
Clear the RXE bit in SICTR to 0
Set the MSSEL bit in SISCR to 1
Reset the master clock source
Set the FSE bit in SICTR to 0
and BPRS=00000 in SISCR
Start the setting FSE=0,
to the RXRST in SISCR
and baud rate in SISCR
Add pulse (0→1→0)
TXE=0 and other bit.
Set BRDV=111
transmit mode?
Change other
Rev. 3.00 Jan. 18, 2008 Page 1415 of 1458
Yes
No
End
Set to disa
Synchronize this LSI internal
frame with FSE=0 if restarting
recept later.
Execute internal initialization
of the bit rate generator
if restarting recept later.
'No' requires further setting
if transmission is not restarted
(No).
When returning to the same
recept mode from here,
go back to No.4, FSE setting,
on this flowchart.
Go to "Start" on each flowchart.
REJ09B0033-0300