MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1035

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

28.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
1
2
Freescale Semiconductor
MGSTAT[1:0]
single fault or double fault but never both). A simultaneous access collision (Flash array read operation returning invalid data
attempted while command running) is indicated when both SFDIF and DFDIF flags are high.
There is a one cycle delay in storing the ECC DFDIF and SFDIF fault flags in this register. At least one NOP is required after
a flash memory read before checking FERSTAT for the occurrence of ECC errors.
The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either
MGBUSY
Offset Module Base + 0x0007
Reset
DFDIF
SFDIF
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
RSVD
Field
1–0
1
0
3
2
W
R
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was
detected in the stored parity and data bits during a Flash array read operation or that a Flash array read operation
returning invalid data was attempted on a Flash block that was under a Flash command operation.
flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF has no effect on DFDIF.
0 No double bit fault detected
1 Double bit fault detected or a Flash array read operation returning invalid data was attempted while command
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag
indicates that a single bit fault was detected in the stored parity and data bits during a Flash array read operation
or that a Flash array read operation returning invalid data was attempted on a Flash block that was under a Flash
command operation.
SFDIF.
0 No single bit fault detected
1 Single bit fault detected and corrected or a Flash array read operation returning invalid data was attempted
Flash Error Status Register (FERSTAT)
0
0
7
Memory Controller Busy Flag — The MGBUSY flag reflects the active state of the Memory Controller
0 Memory Controller is idle
1 Memory Controller is busy executing a Flash command (CCIF = 0)
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error
is detected during execution of a Flash command or during the Flash reset sequence. See
“Flash Command
running
while command running
= Unimplemented or Reserved
0
0
6
Figure 28-12. Flash Error Status Register (FERSTAT)
Table 28-15. FSTAT Field Descriptions (continued)
Description,” and
1
The SFDIF flag is cleared by writing a 1 to SFDIF. Writing a 0 to SFDIF has no effect on
Table 28-16. FERSTAT Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
5
0
0
Section 28.6,
0
0
4
Description
Description
“Initialization” for details.
.
0
0
3
240 KByte Flash Module (S12FTMRG240K2V1)
0
0
2
2
DFDIF
0
1
Section 28.4.6,
1
The DFDIF
SFDIF
0
0
.
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