MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 407

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
FRZ[1:0]
Field
FIFO
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1–0
2
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC10B12C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
VRH = 5.12 Volts
VRL = 0 Volts
Input Signal
5.120 Volts
0.022
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.003
0.002
0.000
...
Table 12-8. ATDCTL3 Field Descriptions (continued)
Table 12-9. Examples of ideal decimal ATD Results
MC9S12G Family Reference Manual, Rev.1.01
Table
(resolution=20mV)
12-11. Leakage onto the storage node and comparator reference capacitors
Codes
8-Bit
255
...
1
1
1
1
1
1
1
0
0
0
0
0
0
Description
(resolution=5mV)
Codes
10-Bit
1023
...
4
4
4
3
3
2
2
2
1
1
1
0
0
Analog-to-Digital Converter (ADC10B12CV2)
407