MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 335

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Addres
0x003A
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
s
10.2.7
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the core logic.
This supply domain is monitored by the Low Voltage Reset circuit.
10.2.8
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit
10.2.9
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
10.3
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1
The S12CPMU registers are shown in
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
CPMUCLKS
CPMUFLG
CPMUPLL
CPMUINT
POSTDIV
REFDIV
CPMU
CPMU
CPMU
Name
SYNR
Memory Map and Registers
VDD — Internal Regulator Output Supply (Core Logic)
VDDF — Internal Regulator Output Supply (NVM Logic)
API_EXTCLK — API external clock output pin
Module Memory Map
W
W
W
W
W
W
W
R
R
R
R
R
R
R
PLLSEL
RTIE
Bit 7
RTIF
VCOFRQ[1:0]
REFFRQ[1:0]
0
0
Figure 10-3. CPMU Register Summary
MC9S12G Family Reference Manual, Rev.1.01
= Unimplemented or Reserved
PORF
PSTP
6
0
0
0
Figure
10-3.
LVRF
FM1
5
0
0
0
0
OSCSEL1
LOCKIE
LOCKIF
COP
FM0
4
0
S12 Clock, Reset and Power Management Unit (S12CPMU)
LOCK
PRE
3
0
0
SYNDIV[5:0]
POSTDIV[4:0]
ILAF
PCE
2
0
0
REFDIV[3:0]
OSCSEL
OSCIE
OSCIF
RTI
1
0
OSCSEL0
UPOSC
Bit 0
COP
0
0
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