MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 352

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
Read: Anytime
352
0x02F1
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
0x02F2
Reset
Reset
LVDS
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
LVIE
LVIF
2
1
0
W
W
R
R
APICLK
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage VDDA is above level V
1 Input voltage VDDA is below level V
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
0
0
0
7
7
Figure 10-16. Low Voltage Control Register (CPMULVCTL)
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Table 10-15. CPMULVCTL Field Descriptions
MC9S12G Family Reference Manual,
5
0
0
5
0
0
LVIA
LVID
APIES
and FPM.
or RPM.
0
0
0
4
4
Description
APIEA
0
0
0
3
3
Rev.1.01
APIFE
LVDS
U
2
2
0
Freescale Semiconductor
APIE
LVIE
0
0
1
1
APIF
LVIF
U
0
0
0