MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 302

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
Access direction can also be used to qualify a match for Comparator B in the same way as described for
Comparator C in
8.4.2.1.3
Comparator A offers address, direction (R/W), access size (word/byte) and data bus comparison.
Table 8-33
lower address is mapped to DBGADH. Access direction can also be used to qualify a match for
Comparator A in the same way as described for Comparator C in
8.4.2.1.4
Comparator A features an NDB control bit, which allows data bus comparators to be configured to either
trigger on equivalence or trigger on difference. This allows monitoring of a difference in the contents of
an address location from an expected value.
When matching on an equivalence (NDB=0), each individual data bus bit position can be masked out by
clearing the corresponding mask bit (DBGADHM/DBGADLM) so that it is ignored in the comparison. A
302
1
SZE
0
0
0
0
0
0
1
1
1
1
1
1
A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.
The comparator address register must contain the exact address from the code.
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Word accesses of ADDR[n] only
Byte accesses of ADDR[n] only
Condition For Valid Match
SZ
X
X
X
X
X
X
0
0
0
0
1
1
lists access considerations with data bus comparison. On word accesses the data byte of the
DBGADHM,
DBGADLM
Comparator A
Comparator A Data Bus Comparison NDB Dependency
$FFFF
$FFFF
$FFFF
$FF00
$00FF
$00FF
$00FF
$FF00
$FF00
$0000
$0000
$0000
Table
Table 8-33. Comparator A Matches When Accessing ADDR[n]
8-31.
Byte
Word
Byte, data(ADDR[n])=DH
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Word
Word, data(ADDR[n])=X, data(ADDR[n+1])=DL
Word, data(ADDR[n])=DH, data(ADDR[n+1])=X
Word, data(ADDR[n])=DH, data(ADDR[n+1])=DL
Byte
Byte, data(ADDR[n])=DH
Table 8-32. Comparator B Access Size Considerations
MC9S12G Family Reference Manual,
DH=DBGADH, DL=DBGADL
Comp B Address RWE
ADDR[n]
ADDR[n]
Access
0
0
SZE
1
1
Rev.1.01
Table
SZ8
No databus comparison
Match data( ADDR[n])
Match data( ADDR[n+1])
Possible unintended match
Match data( ADDR[n], ADDR[n+1])
Possible unintended match
No databus comparison
Match only data at ADDR[n+1]
Match only data at ADDR[n]
Match data at ADDR[n] & ADDR[n+1]
No databus comparison
Match data at ADDR[n]
0
1
8-31.
MOVW #$WORD ADDR[n]
MOVB #$BYTE ADDR[n]
Comment
LDAB ADDR[n]
LDD ADDR[n]
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Examples