MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 981

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

27.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
Freescale Semiconductor
Offset Module Base + 0x0005
IGNSF
Reset
FDFD
FSFD
CCIE
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7
4
1
0
W
R
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Error Configuration Register (FERCNFG)
0
0
7
generated
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
27.3.2.8).
27.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
27.3.2.6)
Figure 27-10. Flash Error Configuration Register (FERCNFG)
= Unimplemented or Reserved
0
0
6
Section
MC9S12G Family Reference Manual, Rev.1.01
Table 27-13. FCNFG Field Descriptions
27.3.2.6)
5
0
0
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
0
0
4
Description
0
0
3
192 KByte Flash Module (S12FTMRG192K2V1)
2
0
0
DFDIE
0
1
Section
Section
27.3.2.7)
SFDIE
27.3.2.7)
0
0
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