MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 610

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (S12SPIV5)
19.3.2.3
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
The baud rate divisor equation is as follows:
The baud rate can be calculated with the following equation:
610
SPPR[2:0]
SPR[2:0]
SPPR2
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
6–4
2–0
0
0
0
0
0
0
0
0
0
0
0
W
R
SPI Baud Rate Preselection Bits — These bits specify the SPI baud rates as shown in
mode, a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Selection Bits — These bits specify the SPI baud rates as shown in
a change of these bits will abort a transmission in progress and force the SPI system into idle state.
SPI Baud Rate Register (SPIBR)
0
0
7
For maximum allowed baud rates, please refer to the SPI Electrical
Specification in the Electricals chapter of this data sheet.
SPPR1
0
0
0
0
0
0
0
0
0
0
0
Table 19-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
= Unimplemented or Reserved
SPPR2
0
6
Baud Rate = BusClock / BaudRateDivisor
BaudRateDivisor = (SPPR + 1) • 2
SPPR0
0
0
0
0
0
0
0
0
1
1
1
Figure 19-5. SPI Baud Rate Register (SPIBR)
MC9S12G Family Reference Manual,
Table 19-5. SPIBR Field Descriptions
SPPR1
5
0
SPR2
0
0
0
0
1
1
1
1
0
0
0
SPPR0
NOTE
SPR1
0
4
0
0
1
1
0
0
1
1
0
0
1
Description
SPR0
(SPR + 1)
0
0
0
1
0
1
0
1
0
1
0
1
0
3
Rev.1.01
Baud Rate
SPR2
Divisor
2
0
128
256
16
32
64
16
2
4
8
4
8
Table
Freescale Semiconductor
SPR1
19-6. In master mode,
0
Table
1
1.5625 Mbit/s
1.5625 Mbit/s
781.25 kbit/s
390.63 kbit/s
195.31 kbit/s
3.125 Mbit/s
3.125 Mbit/s
97.66 kbit/s
Baud Rate
12.5 Mbit/s
6.25 Mbit/s
6.25 Mbit/s
19-6. In master
Eqn. 19-1
Eqn. 19-2
SPR0
0
0