MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 384

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Analog-to-Digital Converter (ADC10B8CV2)
Read: Anytime
Write: Anytime
384
Module Base + 0x0003
S8C, S4C,
S2C, S1C
FRZ[1:0]
Reset
Field
FIFO
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
DJM
6–3
1–0
7
2
W
R
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 11-9
Conversion Sequence Length — These bits control the number of conversions per sequence.
shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
to HC12 family.
Result Register FIFO Mode — If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the first conversion appears in the first result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
file. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
file, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the first
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag clear mode
may be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC10B8C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
Background Debug Freeze Enable — When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
0
7
gives example ATD results for an input signal range between 0 and 5.12 Volts.
S8C
= Unimplemented or Reserved
0
6
Figure 11-6. ATD Control Register 3 (ATDCTL3)
MC9S12G Family Reference Manual,
Table 11-8. ATDCTL3 Field Descriptions
Table
S4C
5
1
11-11. Leakage onto the storage node and comparator reference capacitors
S2C
0
4
Description
S1C
0
3
Rev.1.01
FIFO
2
0
Freescale Semiconductor
FRZ1
0
1
Table 11-10
FRZ0
0
0