MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 647

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

20.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the flag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set.
20.3.2.14 Timer Input Capture/Output Compare Registers High and Low 0–7
1
Freescale Semiconductor
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
TOF
7
W
R
Reset
Reset
W
W
R
R
TOF
Timer Overflow Flag — Set when 16-bit free-running timer overflows from 0xFFFF to 0x0000. Clearing this bit
requires writing a one to bit 7 of TFLG2 register while the TEN bit of TSCR1 or PAEN bit of PACTL is set to one
(See also TCRE control bit explanation.)
(TCxH and TCxL)
0
7
Figure 20-22. Timer Input Capture/Output Compare Register x High (TCxH)
Figure 20-23. Timer Input Capture/Output Compare Register x Low (TCxL)
Bit 15
Bit 7
15
0
0
7
Unimplemented or Reserved
0
0
6
Bit 14
Figure 20-21. Main Timer Interrupt Flag 2 (TFLG2)
Bit 6
14
0
0
6
MC9S12G Family Reference Manual, Rev.1.01
Table 20-17. TRLG2 Field Descriptions
5
0
0
Bit 13
Bit 5
13
0
0
5
0
0
4
Bit 12
Bit 4
12
0
0
4
Description
0
0
3
Bit 11
Bit 3
11
0
0
3
2
0
0
Bit 10
Bit 2
10
0
0
2
Timer Module (TIM16B8CV3)
0
0
1
Bit 9
Bit 1
0
0
9
1
Bit 8
0
0
Bit 0
0
0
0
0
0
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