MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 293

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
8.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
register bytes (three address bus compare registers and a control register). Comparator C consists of four
register bytes (three address bus compare registers and a control register).
Each set of comparator registers can be accessed using the COMRV bits in the DBGC1 register.
Unimplemented registers (e.g. Comparator B data bus and data bus masking) read as zero and cannot be
written. The control register for comparator B differs from those of comparators A and C.
8.3.2.8.1
The contents of this register bits 7 and 6 differ depending upon which comparator registers are visible in
the 8-byte window of the DBG module register address map.
Freescale Semiconductor
Address: 0x0028
0x002A
0x002B
0x002C
0x002D
0x002E
0x0028
0x0029
0x002F
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
SZE
Comparator Register Descriptions
0
7
Debug Comparator Control Register (DBGXCTL)
Figure 8-13. Debug Comparator Control Register DBGACTL (Comparator A)
DATA HIGH COMPARATOR
DATA LOW COMPARATOR
ADDRESS MEDIUM
DATA HIGH MASK
DATA LOW MASK
ADDRESS HIGH
ADDRESS LOW
SZ
= Unimplemented or Reserved
0
6
CONTROL
MC9S12G Family Reference Manual, Rev.1.01
Table 8-20. Comparator Register Layout
TAG
5
0
BRK
0
4
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
RW
0
3
RWE
2
0
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparators A,B and C
Comparator A only
Comparator A only
Comparator A only
Comparator A only
S12S Debug Module (S12SDBG)
NDB
0
1
COMPE
0
0
293