MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 487

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
Freescale Semiconductor
Module Base + 0x0000
Read: Anytime
Write: Anytime when out of initialization mode; exceptions are read-only RXACT and SYNCH, RXFRM (which is set by the
module only), and INITRQ (which is also writable in initialization mode)
CSWAI
RXFRM
SYNCH
RXACT
TIME
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7
6
5
4
3
Reset:
2
W
R
Received Frame Flag — This bit is read and clear only. It is set when a receiver has received a valid message
correctly, independently of the filter configuration. After it is set, it remains set until cleared by software or reset.
Clearing is done by writing a 1. Writing a 0 is ignored. This bit is not valid in loopback mode.
0 No valid message was received since last clearing this flag
1 A valid message was received since last clearing of this flag
Receiver Active Status — This read-only flag indicates the MSCAN is receiving a message
controlled by the receiver front end. This bit is not valid in loopback mode.
0 MSCAN is transmitting or idle
1 MSCAN is receiving a message (including when arbitration is lost)
CAN Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling all
the clocks at the CPU bus interface to the MSCAN module.
0 The module is not affected during wait mode
1 The module ceases to be clocked during wait mode
Synchronized Status — This read-only flag indicates whether the MSCAN is synchronized to the CAN bus and
able to participate in the communication process. It is set and cleared by the MSCAN.
0 MSCAN is not synchronized to the CAN bus
1 MSCAN is synchronized to the CAN bus
Timer Enable — This bit activates an internal 16-bit wide free running timer which is clocked by the bit clock rate.
If the timer is enabled, a 16-bit time stamp will be assigned to each transmitted/received message within the
active TX/RX buffer. Right after the EOF of a valid message on the CAN bus, the time stamp is written to the
highest bytes (0x000E, 0x000F) in the appropriate buffer (see
Storage”). The internal timer is reset (all bits set to 0) when disabled. This bit is held low in initialization mode.
0 Disable internal MSCAN timer
1 Enable internal MSCAN timer
RXFRM
The CANCTL0 register, except WUPE, INITRQ, and SLPRQ, is held in the
reset state when the initialization mode is active (INITRQ = 1 and
INITAK = 1). This register is writable again as soon as the initialization
mode is exited (INITRQ = 0 and INITAK = 0).
0
7
= Unimplemented
RXACT
Figure 16-4. MSCAN Control Register 0 (CANCTL0)
Table 16-3. CANCTL0 Register Field Descriptions
0
6
MC9S12G Family Reference Manual, Rev.1.01
CSWAI
0
5
NOTE
SYNCH
0
4
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
TIME
Section 16.3.3, “Programmer’s Model of Message
0
3
WUPE
2
0
Access: User read/write
SLPRQ
0
1
1
. The flag is
INITRQ
0
1
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