MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 327

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Chapter 10
S12 Clock, Reset and Power Management Unit (S12CPMU)
Revision History
10.1
This specification describes the function of the Clock, Reset and Power Management Unit (S12CPMU).
10.1.1
The Pierce Oscillator (XOSCLCP) contains circuitry to dynamically control current gain in the output
amplitude. This ensures a signal with low harmonic distortion, low power and good noise immunity.
Freescale Semiconductor
Number
Version
V04.09
V04.10
V04.11
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
The Pierce oscillator (XOSCLCP) provides a robust, low-noise and low-power external clock
source. It is designed for optimal start-up margin with typical quartz crystals and ceramic
resonators.
The Voltage regulator (IVREG) operates from the range 3.13V to 5.5V. It provides all the required
chip internal voltages and voltage monitors.
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
The Internal Reference Clock (IRC1M) provides a1MHz clock.
Supports quartz crystals or ceramic resonators from 4MHz to 16MHz.
High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Revision
23 Aug 10
Introduction
22 Jun 10
01 Jul 10
Date
Features
Effective
23 Aug 10
22 Jun 10
01 Jul 10
Date
MC9S12G Family Reference Manual, Rev.1.01
Author
Changed IP-Name from OSCLCP to XOSCLCP, added
OSCCLK_LCP clock name
updated description of
Removed feature of adaptive oscillator filter. Register bits 6 and 4to
0in the CPMUOSC register are marked reserved and do not alter.
Added TC trimming to feature list
Description of Changes
Section 10.2.2, “EXTAL and
intoFigure 10-1
and
Figure 10-2
XTAL.
327

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