MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 207

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
1
2.4.3.63
2.4.3.64
Freescale Semiconductor
Address 0x027E (G1, G2)
Address 0x027E (G3)
Address 0x027F
PIF0AD
Read: Anytime
Write: Anytime, write 1 to clear
Read: Anytime
Write: Anytime
Field
Reset
Reset
Reset
7-0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
W
R
R
R
PIF0AD7
PIF1AD7
Port AD interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
Port AD Interrupt Flag Register (PIF0AD)
0
0
0
Port AD Interrupt Flag Register (PIF1AD)
0
7
7
7
Section 2.4.2.1, “Block Register Map
PIF0AD6
PIF1AD6
0
0
0
0
6
6
6
Figure 2-62. Port AD Interrupt Flag Register (PIF0AD)
Figure 2-63. Port AD Interrupt Flag Register (PIF1AD)
Table 2-90. PIF0AD Register Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
PIF0AD5
PIF1AD5
0
0
0
0
5
5
5
(G1)”). This can be a rising or a falling edge based on the state of the
PIF0AD4
PIF1AD4
0
0
0
0
4
4
4
Description
PIF0AD3
PIF0AD3
PIF1AD3
0
0
0
3
3
3
PIF0AD2
PIF0AD2
PIF1AD2
2
0
2
0
2
0
Port Integration Module (S12GPIMV0)
PIF0AD1
PIF0AD1
PIF1AD1
Access: User read/write
Access: User read/write
Access: User read/write
0
0
0
1
1
1
PIF0AD0
PIF0AD0
PIF1AD0
0
0
0
0
0
0
207
1
1
1