MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 549

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

according to the polarity bit. The counter is also cleared at the end of the effective period (see
Section 17.4.2.5, “Left Aligned Outputs”
details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the
PWMCNTx register. For more detailed information on the operation of the counters, see
“PWM Timer
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or
high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by
16-bit access to maintain data coherency.
1
Read: Anytime
Write: Anytime (any value written causes PWM counter to be reset to $00).
17.3.2.11 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
See
Freescale Semiconductor
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
•
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Section 17.4.2.3, “PWM Period and Duty”
W
R
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
Bit 7
0
0
7
Counters”.
Writing to the counter while the channel is enabled can cause an irregular
PWM cycle to occur.
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Figure 17-12. PWM Channel Counter Registers (PWMCNTx)
0
0
6
6
MC9S12G Family Reference Manual, Rev.1.01
5
0
0
5
and
Section 17.4.2.6, “Center Aligned Outputs”
for more information.
NOTE
NOTE
0
0
4
4
0
0
3
3
Pulse-Width Modulator (S12PWM8B8CV2)
2
0
0
2
0
0
1
1
Section 17.4.2.4,
for more
Bit 0
0
0
0
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