MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 493

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
Freescale Semiconductor
Module Base + 0x0004
RSTAT[1:0]
Read: Anytime
Write: Anytime when not in initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are read-only; write of 1 clears
flag; write of 0 is ignored
WUPIF
CSCIF
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
5-4
7
6
Reset:
W
R
Wake-Up Interrupt Flag — If the MSCAN detects CAN bus activity while in sleep mode (see
“MSCAN Sleep
(CANCTL0)”), the module will set WUPIF. If not masked, a wake-up interrupt is pending while this flag is set.
0 No wake-up activity observed while in sleep mode
1 MSCAN detected activity on the CAN bus and requested wake-up
CAN Status Change Interrupt Flag — This flag is set when the MSCAN changes its current CAN bus status
due to the actual value of the transmit error counter (TEC) and the receive error counter (REC). An additional
4-bit (RSTAT[1:0], TSTAT[1:0]) status register, which is split into separate sections for TEC/REC, informs the
system on the actual CAN bus status (see
(CANRIER)”). If not masked, an error interrupt is pending while this flag is set. CSCIF provides a blocking
interrupt. That guarantees that the receiver/transmitter status bits (RSTAT/TSTAT) are only updated when no
CAN status change interrupt is pending. If the TECs/RECs change their current value after the CSCIF is
asserted, which would cause an additional state change in the RSTAT/TSTAT bits, these bits keep their status
until the current CSCIF interrupt is cleared again.
0 No change in CAN bus status occurred since last interrupt
1 MSCAN changed current CAN bus status
Receiver Status Bits — The values of the error counters control the actual CAN bus status of the MSCAN. As
soon as the status change interrupt flag (CSCIF) is set, these bits indicate the appropriate receiver related CAN
bus status of the MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
00 RxOK: 0 ≤ receive error counter ≤ 96
01 RxWRN: 96 < receive error counter ≤ 127
10 RxERR: 127 < receive error counter
11 Bus-off
WUPIF
The CANRFLG register is held in the reset state
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
0
7
1
: transmit error counter > 255
Figure 16-8. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
Mode,”) and WUPE = 1 in CANTCTL0 (see
CSCIF
Table 16-11. CANRFLG Register Field Descriptions
0
6
MC9S12G Family Reference Manual, Rev.1.01
RSTAT1
0
5
Section 16.3.2.6, “MSCAN Receiver Interrupt Enable Register
RSTAT0
NOTE
0
4
Description
Freescale’s Scalable Controller Area Network (S12MSCANV3)
TSTAT1
Section 16.3.2.1, “MSCAN Control Register 0
1
0
3
when the initialization
TSTAT0
2
0
Access: User read/write
OVRIF
0
1
Section 16.4.5.5,
RXF
0
0
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1