MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 351

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Read: Anytime
Write: Only in Special Mode
10.3.2.12 S12CPMU COP Timer Arm/Reset Register (CPMUARMCOP)
This register is used to restart the COP time-out period.
Read: Always reads $00
Write: Anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
10.3.2.13 Low Voltage Control Register (CPMULVCTL)
The CPMULVCTL register allows the configuration of the low-voltage detect features.
Freescale Semiconductor
0x003E
0x003F
Reset
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W ARMCOP-Bit
R
R
Writing any value other than $55 or $AA causes a COP reset. To restart the COP time-out period
write $55 followed by a write of $AA. These writes do not need to occur back-to-back, but the
sequence ($55, $AA) must be completed prior to COP end of time-out period to avoid a COP reset.
Sequences of $55 writes are allowed. When the WCOP bit is set, $55 and $AA writes must be done
in the last 25% of the selected time-out period; writing any value in the first 75% of the selected
period will cause a COP reset.
0
0
0
7
0
7
7
ARMCOP-Bit
= Unimplemented or Reserved
0
0
0
6
0
6
6
Figure 10-15. S12CPMU CPMUARMCOP Register
Figure 10-14. Reserved Register (CPMUTEST1)
MC9S12G Family Reference Manual, Rev.1.01
ARMCOP-Bit
5
0
0
5
0
5
0
ARMCOP-Bit
0
0
0
4
0
4
4
ARMCOP-Bit
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
0
0
3
0
3
3
ARMCOP-Bit
2
0
0
2
0
2
0
ARMCOP-Bit
0
0
0
1
0
1
1
ARMCOP-Bit
0
0
0
0
0
0
0
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