MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 288

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
8.3.2.6
Read: Anytime
Write: Never
288
Address: 0x0026
CNT[5:0]
Bit[15:0]
Reset
Field
Field
15–0
POR
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
TBF
5–0
7
W
R
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the
Trace Buffer may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer
which points to the next address to be read. When the ARM bit is set the trace buffer is locked to prevent reading.
The trace buffer can only be unlocked for reading by writing to DBGTB with an aligned word write when the
module is disarmed. The DBGTB register can be read only as an aligned word, any byte reads or misaligned
access of these registers return 0 and do not cause the trace buffer pointer to increment to the next trace buffer
address. Similarly reads while the debugger is armed or with the TSOURCE bit clear, return 0 and do not affect
the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer contents.
TBF
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was
last armed. If this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF
bit is cleared when ARM in DBGC1 is written to a one. The TBF is cleared by the power on reset initialization.
Other system generated resets have no affect on this bit
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
Table 8-12
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The DBGCNT
register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus should a reset
occur during a debug session, the DBGCNT register still indicates after the reset, the number of valid trace buffer
entries stored before the reset occurred. The DBGCNT register is not decremented when reading from the trace
buffer.
Debug Count Register (DBGCNT)
—
0
7
TBF
0
shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
—
= Unimplemented or Reserved
0
0
6
CNT[5:0]
000000
Figure 8-8. Debug Count Register (DBGCNT)
MC9S12G Family Reference Manual,
Table 8-11. DBGCNT Field Descriptions
Table 8-10. DBGTB Field Descriptions
Table 8-12. CNT Decoding Table
—
5
0
—
0
4
Description
Description
—
No data valid
0
3
Description
Rev.1.01
CNT
—
2
0
Freescale Semiconductor
—
0
1
—
0
0