MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 369

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

10.5
10.5.1
All reset sources are listed in
priorities.
10.5.2
Upon detection of any reset of
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 10-27
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Resets
Sampled RESET Pin
General
Description of Reset Operation
shows which vector will be fetched.
(256 cycles after
While System Reset is asserted the PLLCLK runs with the frequency
f
VCORST
release)
1
1
1
0
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
External pin RESET
Clock Monitor Reset
.
Reset Source
COP Reset
Table
Table
Oscillator monitor
MC9S12G Family Reference Manual, Rev.1.01
Table 10-27. Reset Vector Selection
fail pending
10-26. Refer to MCU specification for related vector addresses and
10-26, an internal circuit drives the RESET pin low for 512 PLLCLK
Table 10-26. Reset Summary
X
0
1
0
NOTE
time out
pending
COP
0
X
1
X
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
S12 Clock, Reset and Power Management Unit (S12CPMU)
Local Enable
None
None
None
None
Illegal Address Reset
Illegal Address Reset
External pin RESET
Clock Monitor Reset
External pin RESET
Vector Fetch
COP Reset
POR
POR
LVR
LVR
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