MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 164

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
Port Integration Module (S12GPIMV0)
2.4.3
This section describes the details of all configuration registers. Every register has the same functionality
in all groups if not specified separately. Refer to the register figures for reserved locations. If not stated
differently, writing to reserved bits has not effect and read returns zero.
2.4.3.1
164
Address 0x0000 (G1)
Address 0x0000 (G2, G3)
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Reset
Reset
Global Address
Register Name
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
R
R
PIF1AD
0x027F
Register Descriptions
PA7
Port A Data Register (PORTA)
0
0
0
7
7
•
•
•
All register read accesses are synchronous to internal clocks
General-purpose data output availability depends on prioritization; input
data registers always reflect the pin status independent of the use
Pull-device availability, pull-device polarity, wired-or mode,
key-wakeup functionality are independent of the prioritization unless
noted differently in section
description”.
W
R
PIF1AD7
PA6
Bit 7
0
0
0
6
6
Table 2-21. Block Register Map (G3) (continued)
Figure 2-2. Port A Data Register (PORTA)
MC9S12G Family Reference Manual,
= Unimplemented or Reserved
PIF1AD6
PA5
6
0
0
0
5
5
PIF1AD5
Section 2.3, “PIM Routing - Functional
5
PA4
NOTE
0
0
0
4
4
PIF1AD4
4
PA3
0
0
0
3
3
PIF1AD3
Rev.1.01
3
PA2
2
0
2
0
0
PIF1AD2
2
Freescale Semiconductor
Access: User read/write
PA1
PIF1AD1
Access: User read only
0
0
0
1
1
1
PIF1AD0
PA0
Bit 0
0
0
0
0
0
1