MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 430
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MC9S12G
Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12G.pdf
(1160 pages)
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Analog-to-Digital Converter (ADC10B16CV2)
13.3.2.4
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
430
Module Base + 0x0003
ACMPIE
ASCIE
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
1
0
W
R
DJM
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
ATD Control Register 3 (ATDCTL3)
0
7
Interrupt will be requested whenever any of the respective CCF flags is set.
S8C
= Unimplemented or Reserved
0
6
ETRIGLE
Table 13-6. ATDCTL2 Field Descriptions (continued)
Figure 13-6. ATD Control Register 3 (ATDCTL3)
0
0
1
1
Table 13-7. External Trigger Configurations
MC9S12G Family Reference Manual,
S4C
5
1
ETRIGP
0
1
0
1
S2C
0
4
Description
External Trigger Sensitivity
S1C
0
3
Falling edge
Rising edge
High level
Low level
Rev.1.01
FIFO
2
0
Freescale Semiconductor
FRZ1
0
1
FRZ0
0
0
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