MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 252

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Interrupt Module (S12SINTV1)
6.5
6.5.1
After system reset, software should:
6.5.2
The interrupt request scheme makes it possible to nest I bit maskable interrupt requests handled by the
CPU.
I bit maskable interrupt requests cannot be interrupted by other I bit maskable interrupt requests per
default. In order to make an interrupt service routine (ISR) interruptible, the ISR must explicitly clear the
I bit in the CCR (CLI). After clearing the I bit, other I bit maskable interrupt requests can interrupt the
current ISR.
An ISR of an interruptible I bit maskable interrupt request could basically look like this:
6.5.3
6.5.3.1
Every I bit maskable interrupt request is capable of waking the MCU from stop or wait mode. To determine
whether an I bit maskable interrupts is qualified to wake-up the CPU or not, the same conditions as in
normal run mode are applied during stop or wait mode:
Since there are no clocks running in stop mode, only interrupts which can be asserted asynchronously can
wake-up the MCU from stop mode.
The X bit maskable interrupt request can wake up the MCU from stop or wait mode at anytime, even if the
X bit in CCR is set
1. The capability of the XIRQ pin to wake-up the MCU with the X bit set may not be available if, for example, the XIRQ pin is
shared with other peripheral modules on the device. Please refer to the Device section of the MCU reference manual for details.
252
1. Initialize the interrupt vector base register if the interrupt vector table is not located at the default
2. Enable I bit maskable interrupts by clearing the I bit in the CCR.
3. Enable the X bit maskable interrupt by clearing the X bit in the CCR.
•
1. Service interrupt, that is clear interrupt flags, copy data, etc.
2. Clear I bit in the CCR by executing the instruction CLI (thus allowing other I bit maskable interrupt
3. Process data
4. Return from interrupt by executing the instruction RTI
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
location (0xFF80–0xFFF9).
I bit maskable interrupt requests can be interrupted by an interrupt request with a higher priority.
requests)
If the I bit in the CCR is set, all I bit maskable interrupts are masked from waking-up the MCU.
Initialization/Application Information
Initialization
Interrupt Nesting
Wake Up from Stop or Wait Mode
CPU Wake Up from Stop or Wait Mode
1
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MC9S12G Family Reference Manual,
Rev.1.01
Freescale Semiconductor