MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 383

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

11.3.2.4
Writes to this register will abort current conversion sequence.
Freescale Semiconductor
Reserved
ETRIGLE
ACMPIE
ETRIGP
ETRIGE
ASCIE
AFFC
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
6
5
4
3
2
1
0
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 11-7
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
ATD Sequence Complete Interrupt Enable
0 ATD Sequence Complete interrupt requests are disabled.
1 ATD Sequence Complete interrupt will be requested whenever SCF=1 is set.
ATD Compare Interrupt Enable — If automatic compare is enabled for conversion n (CMPE[n]=1 in ATDCMPE
register) this bit enables the compare interrupt. If the CCF[n] flag is set (showing a successful compare for
conversion n), the compare interrupt is triggered.
0 ATD Compare interrupt requests are disabled.
1 For the conversions in a sequence for which automatic compare is enabled (CMPE[n]=1), an ATD Compare
ATD Control Register 3 (ATDCTL3)
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
Interrupt will be requested whenever any of the respective CCF flags is set.
for details.
ETRIGLE
0
0
1
1
Table 11-7. External Trigger Configurations
MC9S12G Family Reference Manual, Rev.1.01
Table 11-6. ATDCTL2 Field Descriptions
Table
ETRIGP
11-5. If the external trigger source is one of the AD channels, the digital
0
1
0
1
Description
External Trigger Sensitivity
Falling edge
Rising edge
High level
Low level
Analog-to-Digital Converter (ADC10B8CV2)
Table 11-7
for details.
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