MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 305

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

8.4.4
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the DBG module has been armed by setting the ARM bit in the DBGC1 register, then
state1 of the state sequencer is entered. Further transitions between the states are then controlled by the
state control registers and channel matches. From Final State the only permitted transition is back to the
disarmed state0. Transition between any of the states 1 to 3 is not restricted. Each transition updates the
SSF[2:0] flags in DBGSR accordingly to indicate the current state.
Alternatively writing to the TRIG bit in DBGSC1, provides an immediate trigger independent of
comparator matches.
Independent of the state sequencer, each comparator channel can be individually configured to generate an
immediate breakpoint when a match occurs through the use of the BRK bits in the DBGxCTL registers.
Thus it is possible to generate an immediate breakpoint on selected channels, whilst a state sequencer
transition can be initiated by a match on other channels. If a debug session is ended by a match on a channel
the state sequencer transitions through Final State for a clock cycle to state0. This is independent of tracing
and breakpoint activity, thus with tracing and breakpoints disabled, the state sequencer enters state0 and
the debug module is disarmed.
8.4.4.1
On entering Final State a trigger may be issued to the trace buffer according to the trace alignment control
as defined by the TALIGN bit (see
TSOURCE bit in DBGTCR is clear then the trace buffer is disabled and the transition to Final State can
only generate a breakpoint request. In this case or upon completion of a tracing session when tracing is
enabled, the ARM bit in the DBGC1 register is cleared, returning the module to the disarmed state0. If
tracing is enabled a breakpoint request can occur at the end of the tracing session. If neither tracing nor
breakpoints are enabled then when the final state is reached it returns automatically to state0 and the debug
module is disarmed.
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
State Sequence Control
Final State
(Disarmed)
State 0
ARM = 0
ARM = 0
Session Complete
(Disarm)
MC9S12G Family Reference Manual, Rev.1.01
ARM = 1
ARM = 0
Figure 8-24. State Sequencer Diagram
Section 8.3.2.3, “Debug Trace Control Register
Final State
State1
State3
S12S Debug Module (S12SDBG)
State2
(DBGTCR)”). If the
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