MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 575

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

18.3.2.7
The SCISR1 and SCISR2 registers provides inputs to the MCU for generation of SCI interrupts. Also,
these registers can be polled by the MCU to check the status of these bits. The flag-clearing procedures
require that the status register be read followed by a read or write to the SCI data register.It is permissible
to execute other instructions between the two steps as long as it does not compromise the handling of I/O,
but the order of operations is important for flag clearing.
Read: Anytime
Write: Has no meaning or effect
Freescale Semiconductor
Module Base + 0x0004
Reset
Field
RWU
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
SBK
1
0
W
R
TDRE
Receiver Wakeup Bit — Standby state
0 Normal operation.
1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes
Send Break Bit — Toggling SBK sends one break character (10 or 11 logic 0s, respectively 13 or 14 logics 0s
if BRK13 is set). Toggling implies clearing the SBK bit before the break character has finished transmitting. As
long as SBK is set, the transmitter continues to send complete break characters (10 or 11 bits, respectively 13
or 14 bits).
0 No break characters
1 Transmit break characters
SCI Status Register 1 (SCISR1)
1
7
the receiver by automatically clearing RWU.
TC
= Unimplemented or Reserved
1
6
Table 18-10. SCICR2 Field Descriptions (continued)
Figure 18-10. SCI Status Register 1 (SCISR1)
MC9S12G Family Reference Manual, Rev.1.01
RDRF
5
0
IDLE
0
4
Description
OR
0
3
Serial Communication Interface (S12SCIV5)
NF
2
0
FE
0
1
PF
0
0
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