MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 310

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12S Debug Module (S12SDBG)
Field2 Bits in Normal and Loop1 Modes
8.4.5.4
310
PC17
PC16
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
CSD
CVA
Pure PC Mode
Bit
Compressed
3
2
1
0
Mode
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode .
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16— In Normal and Loop1 mode this bit corresponds to program counter bit 16.
Trace Buffer Organization (Compressed Pure PC mode)
Table 8-39. Trace Buffer Organization Example (Compressed PurePC mode)
Number
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line
Field 3
2-bits
00
11
01
00
10
00
MC9S12G Family Reference Manual,
Table 8-38. PCH Field Descriptions
Figure 8-26. Information Bits PCH
CSD
Bit 3
Field 2
6-bits
PC4
0
0
Bit 2
CVA
PC1 (Initial 18-bit PC Base Address)
PC6 (New 18-bit PC Base Address)
PC9 (New 18-bit PC Base Address)
Description
PC17
Bit 1
Field 1
PC16
6-bits
Bit 0
Rev.1.01
PC3
PC8
0
Freescale Semiconductor
Field 0
6-bits
PC2
PC5
PC7