MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 338

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.2
The CPMUREFDIV register provides a finer granularity for the PLL multiplier steps when using the
external oscillator as reference.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
The REFFRQ[1:0] bits are used to configure the internal PLL filter for optimal stability and lock time. For
correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK
frequency as shown in
If IRC1M is selected as REFCLK (OSCE=0) the PLL filter is fixed configured for the 1MHz <= f
2MHz range. The bits can still be written but will have no effect on the PLL filter configuration.
For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking
and/or insufficient stability).
338
0x0035
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
If XOSCLCP is enabled (OSCE=1)
If XOSCLCP is disabled (OSCE=0)
W
R
S12CPMU Reference Divider Register (CPMUREFDIV)
0
7
REFFRQ[1:0]
Write to this register clears the LOCK and UPOSC status bits.
Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV)
Table
0
6
10-2.
Table 10-1. VCO Clock Frequency Selection
VCOCLK Frequency Ranges
MC9S12G Family Reference Manual,
5
0
0
Reserved
f REF
f REF
=
=
NOTE
------------------------------------
(
f IRC1M
0
0
4
REFDIV
f OSC
+
1
)
1
3
VCOFRQ[1:0]
Rev.1.01
11
2
1
REFDIV[3:0]
Freescale Semiconductor
1
1
REF
1
0
<=