MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 646

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timer Module (TIM16B8CV3)
20.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
646
C[7:0]F
Reset
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7:0
unavailable bits return a zero.
W
R
C7F
Input Capture/Output Compare Channel “x” Flag — These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding flag bit while TEN or PAEN is set to
one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
0
7
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
channel (0x0010–0x001F) will cause the corresponding channel flag CxF to be cleared.
C6F
0
6
Figure 20-20. Main Timer Interrupt Flag 1 (TFLG1)
PR2
0
0
0
0
1
1
1
1
MC9S12G Family Reference Manual,
Table 20-16. TRLG1 Field Descriptions
Table 20-15. Timer Clock Selection
C5F
5
0
PR1
0
0
1
1
0
0
1
1
C4F
NOTE
0
4
PR0
Description
0
1
0
1
0
1
0
1
C3F
0
3
Bus Clock / 128
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 1
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Timer Clock
Rev.1.01
C2F
2
0
Freescale Semiconductor
C1F
0
1
C0F
0
0