MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 1090

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Electrical Characteristics
This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.
1
2
A.3.2
Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.
A.3.2.1
PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it
is recommended to configure PortAD pins as outputs only for low frequency, low load outputs. The impact
on ATD accuracy is load dependent and not specified. The values specified are valid under condition that
no PortAD output drivers switch during conversion.
A.3.2.2
Due to the input pin leakage current as specified in conjunction with the source resistance there will be a
voltage drop from the signal source to the ATD input. The maximum source resistance R
in an error (10-bit resolution) of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If device or
operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source
resistance of up to 10Kohm are allowed.
1090
Supply voltage 3.13 V < V
Num C
Full accuracy is not guaranteed when differential voltage is less than 4.50 V
The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.
1
2
3
4
5
8
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
D Reference potential
D Voltage difference V
D Voltage difference V
C Differential reference voltage
C ATD Clock Frequency (derived from bus clock via the
D
prescaler bus)
ATD Conversion Period
12 bit resolution:
10 bit resolution:
8 bit resolution:
Factors Influencing Accuracy
Low
High
Port AD Output Drivers Switching
Source Resistance
DDA
< 5.5 V, -40
DDX
SSX
2
to V
to V
Rating
Table A-14. ATD Operating Characteristics
MC9S12G Family Reference Manual,
SSA
DDA
1
o
C < T
J
< 150
o
C
N
N
V
Symbol
N
f
∆
∆
ATDCLk
RH
CONV12
CONV10
CONV8
V
V
VDDX
VSSX
RH
RL
-V
RL
Rev.1.01
V
–2.35
V
–0.1
3.13
0.25
DDA
Min
20
19
17
SSA
/2
Typ
5.0
—
—
0
0
Freescale Semiconductor
S
specifies results
V
V
Max
DDA
0.1
0.1
5.5
8.0
42
41
39
DDA
/2
Cycles
clock
MHz
Unit
ATD
V
V
V
V
V