MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 135

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
PT4
PT3-PT2
PT1
PT0
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
• 48/64/100 LQFP: The TIM channel 4 signal is mapped to this pin when used with the timer function.
• Signal priority:
• Except 20 TSSOP: The TIM channels 3 and 2 signal are mapped to these pins when used with the
• Signal priority:
• Except 100 LQFP: The IRQ signal is mapped to this pin when used with the IRQ interrupt function. If
• The TIM channel 1 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
• Except 100 LQFP: The XIRQ signal is mapped to this pin when used with the XIRQ interrupt
• The TIM channel 0 signal is mapped to this pin when used with the timer function. The TIM forces the
• Signal priority:
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
48/64/100 LQFP: IOC4 > GPO
timer function. The TIM forces the I/O state to be an output for a timer port associated with an enabled
output compare.
Except 20 TSSOP: IOC3-2 > GPO
enabled (IRQCR[IRQEN]=1) the I/O state of the pin is forced to be an input.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC1 > GPO
Others: IRQ > IOC1 > GPO
function.The interrupt is enabled by clearing the X mask bit in the CPU Condition Code register. The
I/O state of the pin is forced to input level upon the first clearing of the X bit and held in this state even
if the bit is set again. A STOP or WAIT recovery with the X bit set (refer to CPU12/CPU12X Reference
Manual) is not available.
I/O state to be an output for a timer port associated with an enabled output compare.
100 LQFP: IOC0 > GPO
Others: XIRQ > IOC0 > GPO
Table 2-11. Port
MC9S12G Family Reference Manual, Rev.1.01
T
Pins PT7-0 (continued)
Port Integration Module (S12GPIMV0)
135