MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 651

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
20.3.2.18 Output Compare Pin Disconnect Register(OCPD)
Read: Anytime
Write: Anytime
All bits reset to zero.
Freescale Semiconductor
This register is available only when channel 7 exists and is reserved if that channel does not exist. Writes to a reserved register
have no functional effect. Reads from a reserved register return zeroes.
Reset
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
R
R
PACNT7
OCPD7
0
0
7
7
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
Reading the pulse accumulator counter registers immediately after an active
Figure 20-27. Pulse Accumulator Count Register Low (PACNTL)
Figure 20-28. Output Compare Pin Disconnect Register (OCPD)
PACNT6
OCPD6
0
0
6
6
MC9S12G Family Reference Manual, Rev.1.01
PACNT5
OCPD5
5
0
5
0
PACNT4
OCPD4
NOTE
0
0
4
4
PACNT3
OCPD3
0
0
3
3
PACNT2
OCPD2
2
0
2
0
Timer Module (TIM16B8CV3)
PACNT1
OCPD1
0
0
1
1
PACNT0
OCPD0
0
0
0
0
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