MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 551

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

To calculate the output duty cycle (high time as a% of period) for a particular channel:
For boundary case programming values, please refer to
1
Read: Anytime
Write: Anytime
17.4
17.4.1
There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These
four clocks are based on the bus clock.
Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA
uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B
as an input and divides it further with a reloadable counter. The rates available for clock SA are software
selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are
available for clock SB. Each PWM channel has the capability of selecting one of four clocks, clock A,
Clock B, clock SA or clock SB.
The block diagram in
Freescale Semiconductor
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
•
•
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
R
Polarity = 0 (PPOL x =0)
Polarity = 1 (PPOLx = 1)
Functional Description
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
PWM Clock Select
Bit 7
1
7
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is zero, the output starts
low and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
Figure 17-15
Figure 17-14. PWM Channel Duty Registers (PWMDTYx)
1
6
6
MC9S12G Family Reference Manual, Rev.1.01
shows the four different clocks and how the scaled clocks are created.
5
1
5
NOTE
1
4
4
Section 17.4.2.8, “PWM Boundary
1
3
3
Pulse-Width Modulator (S12PWM8B8CV2)
2
1
2
1
1
1
Cases”.
Bit 0
1
0
551