MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 503

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
Module Base + 0x0018 to Module Base + 0x001B
1
Module Base + 0x0010 to Module Base + 0x0013
16.3.2.17 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
AC[7:0]
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
7-0
Figure 16-21. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Figure 16-20. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
W
R
W
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
Writing to this register when in special modes can alter the MSCAN
functionality.
AC7
AC7
0
7
0
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 16-22. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
AC6
0
6
0
6
MC9S12G Family Reference Manual, Rev.1.01
AC5
AC5
0
5
0
5
AC4
AC4
0
4
Description
0
4
Freescale’s Scalable Controller Area Network (S12MSCANV3)
AC3
AC3
0
3
0
3
AC2
AC2
0
2
0
2
Access: User read/write
Access: User read/write
Section 16.3.3.1,
AC1
Section 16.4.3,
AC1
1
0
0
1
AC0
AC0
0
0
0
0
503
1
1