MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 440

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Analog-to-Digital Converter (ADC10B16CV2)
13.3.2.12.1 Left Justified Result Data (DJM=0)
Table 13-21
result registers for left justified data. Compare is always done using all 12 bits of both the conversion result
and the compare value in ATDDRn.
13.3.2.12.2 Right Justified Result Data (DJM=1)
440
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
Module Base +
0x0010 = ATDDR0, 0x0012 = ATDDR1, 0x0014 = ATDDR2, 0x0016 = ATDDR3
0x0018 = ATDDR4, 0x001A = ATDDR5, 0x001C = ATDDR6, 0x001E = ATDDR7
0x0020 = ATDDR8, 0x0022 = ATDDR9, 0x0024 = ATDDR10, 0x0026 = ATDDR11
0x0028 = ATDDR12, 0x002A = ATDDR13, 0x002C = ATDDR14, 0x002E = ATDDR15
Reset
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
W
W
R
R
15
15
0
0
0
shows how depending on the A/D resolution the conversion result is transferred to the ATD
= Unimplemented or Reserved
= Unimplemented or Reserved
14
14
0
0
0
Figure 13-15. Right justified ATD conversion result register (ATDDRn)
Figure 13-14. Left justified ATD conversion result register (ATDDRn)
13
13
0
0
0
resolution
10-bit data
8-bit data
Table 13-21. Conversion result mapping to ATDDRn
A/D
12
12
0
0
0
MC9S12G Family Reference Manual,
11
11
0
0
0
0
DJM
Result-Bit[11:0]
10
10
0
0
Result-Bit[11:4] = conversion result,
Result-Bit[3:0]=0000
Result-Bit[11:2] = conversion result,
Result-Bit[1:0]=00
conversion result mapping to
0
0
9
9
0
0
8
8
0
0
7
7
Result-Bit[11:0]
0
0
6
6
Rev.1.01
ATDDRn
0
0
5
5
0
0
4
4
0
0
0
3
3
Freescale Semiconductor
2
0
0
2
0
0
0
0
1
1
0
0
0
0
0

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