MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 550

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Pulse-Width Modulator (S12PWM8B8CV2)
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
For boundary case programming values, please refer to
1
Read: Anytime
Write: Anytime
17.3.2.12 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
See
550
This register is available only when the corresponding channel exists and is reserved if that channel does not exist. Writes to
a reserved register have no functional effect. Reads from a reserved register return zeroes.
Reset
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This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Section 17.4.2.3, “PWM Period and Duty”
W
R
Left aligned output (CAEx = 0)
Center Aligned Output (CAEx = 1)
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
PWMx Period = Channel Clock Period * PWMPERx
PWMx Period = Channel Clock Period * (2 * PWMPERx)
Bit 7
1
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Figure 17-13. PWM Channel Period Registers (PWMPERx)
1
6
6
MC9S12G Family Reference Manual,
5
1
5
for more information.
NOTE
1
4
4
Section 17.4.2.8, “PWM Boundary
1
3
3
Rev.1.01
2
1
2
Freescale Semiconductor
1
1
1
Cases”.
Bit 0
1
0