MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 361

• Manufacturer Part Number: MC9S12G
• Description: Ignores external trigger. Performs one conversion sequence and stops.
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

OSCPINS_EN
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
10.3.2.20 S12CPMU Protection Register (CPMUPROT)
This register protects the following clock configuration registers from accidental overwrite:
Freescale Semiconductor
0x02FA
Reserved
Reserved
Reset
OSCE
Field
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
4-0
7
6
5
W
R
OSCE
Oscillator Enable Bit — This bit enables the external oscillator (XOSCLCP). The UPOSC status bit in the
CPMUFLG register indicates when the oscillation is stable and OSCCLK can be selected as Bus Clock or source
of the COP or RTI. A loss of oscillation will lead to a clock monitor reset.
0 External oscillator is disabled.
1 External oscillator is enabled.Clock monitor is enabled.External oscillator is qualified by PLLCLK
Note: When starting up the external oscillator (either by programming OSCE bit to 1 or on exit from Full Stop
Do not alter this bit from its reset value. It is for Manufacturer use only and can change the PLL behavior.
Oscillator Pins EXTAL and XTAL Enable Bit
If OSCE=1 this read-only bit is set. It can only be cleared with the next reset.
Enabling the external oscillator reserves the EXTAL and XTAL pins exclusively for oscillator application.
0 EXTAL and XTAL pins are not reserved for oscillator.
1 EXTAL and XTAL pins exclusively reserved for oscillator.
Do not alter these bits from their reset value. It is for Manufacturer use only and can change the PLL behavior.
0
7
Write to this register clears the LOCK and UPOSC status bits.
REFCLK for PLL is IRCCLK.
REFCLK for PLL is the external oscillator clock divided by REFDIV.
Mode with OSCE bit already 1) the software must wait for a minimum time equivalent to the startup-time
of the external oscillator t
Reserved
Figure 10-27. S12CPMU Oscillator Register (CPMUOSC)
0
6
Table 10-24. CPMUOSC Field Descriptions
MC9S12G Family Reference Manual, Rev.1.01
OSCPINS_E
N
5
0
UPOSC
before entering Pseudo Stop Mode.
NOTE.
0
4
Description
S12 Clock, Reset and Power Management Unit (S12CPMU)
0
3
Reserved]
2
0
0
1
0
0
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