MC9S12G FREESCALE [Freescale Semiconductor, Inc], MC9S12G Datasheet - Page 542

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MC9S12G

Manufacturer Part Number
MC9S12G
Description
Ignores external trigger. Performs one conversion sequence and stops.
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Pulse-Width Modulator (S12PWM8B8CV2)
Read: Anytime
Write: Anytime
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
17.3.2.3
Each PWM channel has a choice of four clocks to use as the clock source for that channel as described
below.
Read: Anytime
Write: Anytime
542
PPOL[7:0]
Reset
Reset
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
Field
7–0
unavailable bits return a zero
W
W
R
R
PPOL7
PCLK7
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
PWM Clock Select Register (PWMCLK)
0
0
7
7
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
reached.
reached.
PCLKL6
PPOL6
0
0
6
6
Figure 17-5. PWM Clock Select Register (PWMCLK)
Figure 17-4. PWM Polarity Register (PWMPOL)
MC9S12G Family Reference Manual,
Table 17-3. PWMPOL Field Descriptions
PPOL5
PCLK5
5
0
5
0
PPOL4
PCLK4
NOTE
NOTE
0
0
4
4
Description
PPOL3
PCLK3
0
0
3
3
Rev.1.01
PPOL2
PCLK2
2
0
2
0
Freescale Semiconductor
PPOL1
PCLK1
0
0
1
1
PPOL0
PCLK0
0
0
0
0

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